This invention is related to a technique and associated integrated circuitry for data signal transmission within a computer or between any electronic devices. In particular, the related application is for, although not limited to, the high speed serial data communication through a Universal Serial Bus (USB) with the industry standard specification of USB 2.0. A related technique of data communication is half duplexing. Some related technologies for logic circuitry are Emitter Coupled Logic (ECL) and Complementary Metal-Oxide-Semiconductor transistor (CMOS).
With the rapid development of information technology, the peripherals of a computer are no longer limited to the following list of traditional elements:
keyboard, mouse, hard disk, optical disk and printer.
In fact, the list of computer peripherals now includes additional elements such as digital camera, digital video camera, digital color scanner, digital audio recording system and so on. As a consequence, the computer is not only used to process classical text information such as in a word processing or a spread sheet application, the computer also needs to process the vast amount of information contained in figures, images and audio titles, etc. In order to deal with such vast amount of information, the computer not only needs a powerful Central Processing Unit (CPU), but also, sometimes even critical, needs a much higher data transmission rate with its peripherals. For example, a high data transmission rate is simply needed between a computer and a high quality digital video camera. For another example, a high data transmission rate is especially important within a computer network system to prevent data congestion.
The hardware conduit of signal transmission between a computer and various electronic devices is called a bus. Physically, a bus consists of a set of ordered signal wires with each of the signal wires having a precise signal definition. Generally the bus can be broadly classified, according to its construction, into two types: parallel interface and serial interface. An example of parallel interface 3 is illustrated in FIG. 1A for signal transmission between a Computer 1 and an electronic device 2. In addition to a number of control signals 4, the parallel interface 3 consists of a group of, in this example, eight (8) parallel data signals D0-D75 carrying bidirectional data signals between the Computer 1 and the electronic device 2. At a particular instant, a data pattern of (01001001) is carried by the parallel data signals D0-D75 as indicated. Under a given data clock rate, the parallel interface 3 can provide a much higher data transmission rate proportional to the number of parallel data signals (in this case 8). However, due to an inherent cross coupling of neighboring parallel data signals, the parallel interface 3 can only reach a shorter transmission distance before the development of excessive noise from the cross coupling effect. As the magnitude of noise from cross coupling is generally proportional to the data clock rate, it follows that, in general, the higher the data clock rate is, the shorter the maximum transmission distance is allowed.
An example of serial interface 30 is illustrated in FIG. 1B for signal transmission between a computer 10 and an electronic device 20. The serial interface 30 consists of, in this example, only two signals: a serial transmitting signal 40 carrying a uni-directional data signal from the computer 10 to the electronic device 20 and a serial receiving signal 45 carrying a uni-directional data signal from the electronic device 20 to the computer 10. Being a serial interface, an example data pattern of (01001001) is carried by the serial transmitting signal 40 with an example transmitting data pattern 50 in the time domain as indicated. Technically, for a long time, the data transmission rate of the serial interface 30 had been limited to 115 Kb/s-230 Kb/s (Kilobits/second), which was only about one eighth of the typical data transmission rate of the parallel interface. However, since 1994 a series of USB (Universal Serial Bus) specifications, targeting a highly flexible serial interface at a data transmission rate much higher than the 115 Kb/s-230 Kb/s, have been published for implementation following discussion and collaboration amongst many established computer and communication manufacturers in the world. For example, one of the specifications is USB1.1 having a data transmission rate of 12 Mb/s(Megabits/second). While the technique of serial interfacing, having to perform such extra tasks as control of transmission timing, bidirectional data transformation between serial and parallel format, bit counting, is more complex than that of parallel interfacing and the serial data transmission rate is inherently lower, the associated benefits support the enthusiastic adoption of USB by the market. For example, with the adoption of differential low level signal technology, the data transmission rate of USB is much improved. As the serial interface has a smaller number of signal wires than the parallel interface, the serial interface is simpler and the cost of its transmission cable is lower. The USB specification also has other benefits like easiness of usage, easiness of connection, multimedia support and self-powering, etc. Additionally, the USB1.1 supports the connection of multiple devices through a single interface cable, the function of PnP (Plug and Play) and is built into the Windows operating system. Therefore, by now, USB1.1 has already been widely adopted in the microcomputer and computer networking industry. More recently, following the USB1.1, a USB2.0 specification was published in 1999 with an even higher data transmission rate of 480 Mb/s while maintaining its compatibility with the USB1.1. Thus, the USB2.0 is expected to further promote the development of peripheral devices for the microcomputer and many components for the data communication industry. As already stated, USB is a serial interface.
At the hardware level, to support such a high and ever growing data transmission rate of USB, the established technology of Emitter Coupled Logic (ECL) represents a natural choice for the base of implementation of the associated transceivers. For those skilled in the art, ECL is a family of high speed digital circuitry based upon bipolar transistors. When its switching transistor is in the state of conduction, the conductive transistor works in a state of non-saturation. Thus, when the conductive transistor is later switched off, there will be no memory effect causing an associated time delay. This means ECL can work at a higher frequency. The cause of this memory effect is the excess minority carriers in the base of the transistor requiring time for recombination with a corresponding number of majority carriers during the switching process. The associated circuit resistance value of ECL is generally low making it highly immune to external noises. The reason is that most noise sources have high output impedance thus only capable of producing a small voltage disturbance on a low resistance load. Thus, in combination with a small logic swing of their output voltage, ECL circuits have achieved, with a propagation delay time under 1 ns, the highest operating frequency of all digital circuits. As the output section of ECL uses an emitter follower structure of low output impedance, ECL is capable of high load driving capacity such as the load from a serial interface cable. With a balanced circuit topology, the transient change of power supply current of ECL is relatively small during a logic switching process that allows the resulting switching noise to be correspondingly small. Again with a balanced circuit topology, the logic output of ECL is complementary that makes it convenient and quick to use. Notwithstanding all the above superior characteristics, ECL does have some drawbacks. For example, its low circuit resistance means higher power consumption for a given supply voltage. As the transistors of ECL operate in a state of no-saturation, the stability of its output voltage level is lower and it is more sensitive to the change of environmental temperature. The small logic swing of ECL output voltage affords an allowable noise amplitude of only 200 mV RMS (Root Mean Square). Realizing these drawbacks of ECL, substantial efforts aimed for its improvement have already been underway. For example, currently the sub-nanosecond ECL integrated circuit employs the technique of compensation for the variation of temperature and supply voltage thus maintaining the normal functionality of the circuit regardless of these variations.
While ECL represents a natural base for the implementation of USB transceivers, a number of incompatibilities between the two still remain to be removed. First, the output voltage amplitude of ECL is fixed at 800 mV peak-peak that is too high compared to the USB specification. Secondly, most computers and peripheral electronic devices nowadays employ CMOS (Complementary Metal Oxide Semiconductor) logic circuits which is not directly interfaceable with ECL. Thirdly, the USB calls for a scheme of communication called half duplexing, which is also not directly compatible with the ECL circuitry. Therefore, with the continuing market advancement of the USB, there is a strong need of improving the ECL technology so that it can be adapted to conform to the USB specification thereby functions as effective USB transceivers.
An object of the present invention is to adapt the ECL technology so that it conforms to the USB specification thereby functions as effective USB transceivers.
More specifically, in the present invention, an emitter resistance network is modified in the ECL circuit to adjust its output voltage amplitude till it meets the USB specification. A number of signal level shifting circuits are added at both the input and output sections of the ECL circuit to make it directly interfaceable with CMOS logic. A collector electrode switch network is also added to the ECL circuit to make it compatible with the communication scheme of half duplexing for the USB.